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summary t c901 04f g ? 201 5 toshiba corporation page 1 rev.1.0 0 20 15/ 12 / 01 TC90104FG multi system video decoder i c th e TC90104FG is a single chip ic that converts analog video signals to digi tal video signals ( itu - r b t. 601 / itu - r b t. 656 or 18bit digital rgb signal). additionally , the TC90104FG has a 3 - channel a/d converter as an analog input interface , and has 3 - line y/c separation and multi - system color decoder functionality. 1. features ? input : cvbs, y /c(s - video), y cb cr, rgb ? multi - color decoder ? adaptive multi - standard detection / sync processing ? synchronous playback / standard identification ? y/c separation : 3 - line ycs (ntsc/pal) bpf processing . (secam) ? picture process y : v - enhance, lti, sharpnes s, noise cancel, contrast, brightness c : tof , acc , color gain, cti, noise cancel rgb : color gain, color offset, gamma correction ? analog rgb input : wqvga to wvga (dot by dot) ? adc - clock phase adjustment (rgb input) ? output : itu - r bt. 601 / itu - r bt. 656 in video , rgb 6bit x 3 in rgb. ? i 2 c - bus control ? p ackage : lqfp 64 p in ( 0.50 mm pitch ) ? power supply : 3.3 v , 2.5 v , 1. 5 v lqfp64 -p- 1010- 0.50e weight : 0.4 g ( typ. )
summary t c901 04f g ? 201 5 toshiba corporation page 2 rev.1.0 0 20 15/ 12 / 01 2. block diagram to explain the function, there are omitted part for function block and applicatio n circuit. 3. pin layout
summary t c901 04f g ? 201 5 toshiba corporation page 3 rev.1.0 0 20 15/ 12 / 01 4. pin descriptions pin no. pin name pin function pin type standard w ithstand v oltage [v] processing at unused time 1 vddda 2.5 v power suppl y for dac vdd 2.5 - 2 pllin input of pll circuit for clock in 2.5 - 3 vddpll 2.5 v power supply for pll circuit vdd 2.5 - 4 vcofil filter terminal for pll circuit b ia s 2.5 - 5 vsspll gnd for pll circuit vss 0 - 6 vddxo power supply for x?tal circuit v dd 2.5 - 7 xoin input for x?tal circuit in 2.5 - 8 xoout output for x?tal circuit out 2.5 - 9 vssxo gnd for x?tal circuit gnd 0 - 10 vdd - d1 1.5 v power supply for logic circuit vdd 1.5 - 11 sda serial data input/output i / o 5 - 12 sc l serial clock input in 5 - 13 reset system reset in 3.3 - 14 vss 1 gnd for logic gnd 0 - 15 enb enable signal output out 3.3 open 16 vd vertical timing signal output out 3.3 open 17 hd horizontal timing signal output out 3.3 open 18 clk clo ck signal output out 3.3 - 19 vdd - io1 3.3 v power supply for i/o circuit vdd 3.3 - 20 b5/y7 b5 / y7 signal output out 3.3 - 21 b4/y6 b4 / y6 signal output out 3.3 - 22 vss 2 gnd for logic gnd 0 - 23 vdd - d2 1.5v power supply for logic circuit vdd 1.5 - 24 b3/y5 b3 / y5 signal output out 3.3 - 25 b2/y4 b2 / y4 signal output out 3.3 - 26 vdd - io2 3.3v power supply for i/o circuit vdd 3.3 - 27 b1/y3 b1 / y3 signal output out 3.3 - 28 b0/y2 b0 / y2 sig nal output out 3.3 - 29 vss3 gnd for logic gnd 0 - 30 g5/y1 g5 / y1 signal output out 3.3 - 31 g4/y0 g4 / y0 signal output out 3.3 - 32 g3 g3 signal output out 3.3 -
summary t c901 04f g ? 201 5 toshiba corporation page 4 rev.1.0 0 20 15/ 12 / 01 pin no. pin name pin function pin type standard w i thstand v oltage [v] processing at unused time 33 g2 g2 signal output out 3.3 - 34 vss 4 gnd for logic gnd 0 - 35 g1/c0 g1 / c0 signal output out 3.3 - 36 g0/c1 g0 / c1 signal output out 3.3 - 37 vdd - d3 1.5 v power supply for logic circuit vdd 1.5 - 38 r5/c2 r5 / c2 signal output out 3.3 - 39 r4/c3 r4 / c3 signal output out 3.3 - 40 vss5 gnd for logic gnd 0 - 41 r3/c4 r3 / c4 signal output out 3.3 - 42 r2/c5 r 2 / c5 signal out put out 3.3 - 43 vdd - io3 3.3 v power supply for i/o circuit vdd 3.3 - 44 r1/c6 r1 / c6 signal output out 3.3 - 45 r0/c7 r0 / c7 signal output out 3.3 - 46 slave sel i 2 c - bus slave - address selector in 3.3 - 47 test2 test terminal (a lways connect to gnd) in 3.3 gnd 48 test1 test terminal (always connect to gnd) in 3.3 gnd 49 vddad1 2.5 v power supply for adc circuit vdd 2.5 - 50 cvbs1 in composite video signal input in 2.5 gnd via 0.1
summary t c901 04f g ? 201 5 toshiba corporation page 5 rev.1.0 0 20 15/ 12 / 01 5. function 5.1 overview ? a nalog in put interface for cvbs (composite video signal), y/c separate signal, component signal (d1/d2), analog rgb signal (d1/d2) and analog rgb signal (wqvga / v ga / wvga) ? multi system 3 - line comb filter (2d ycs) ? multi system video decoder and sync processing ? c olor system detection (selectable auto detection or manual setting) ? picture processing function ? adjustable the clock phase of adc in analog rgb input mode ? d igital output interface for itu - r b t. 601/656 and 18bit rgb signal when input signal is analog rgb, output signal is digital rgb only. 5.2 input signal 5.2.1 input signal list input signal format frequency effective pixels total pixels fh[khz] fv[hz] fs [ mhz] horizontal vertical horizontal vertical cvbs ntsc 15.75/15.734 60/59.94 27 720 240 858 262.5 pal 15.625 50 27 720 288 864 312.5 y/c ntsc 15.75/15.734 60/59.94 27 720 240 858 262.5 pal 15.625 50 27 720 288 864 312.5 ycbcr d1 480i 15.75/ 15.734 60 27 720 240 858 262.5 576i 15.625 50 27 720 288 864 312.5 d2 480p 31.5 /31.469 60 27 720 480 858 525 576p 31.25 50 27 720 576 864 625 rgb d1 480i 15.75/ 15.734 60 27 720 240 858 262.5 576i 15.625 50 27 720 288 864 312.5 d2 480p 31.5 /31.469 60 2 7 720 480 858 525 576p 31.25 50 27 720 576 864 625 rgb wqvga (400x234) 15.734 60 fh508 400 234 508 262 15.625 50 fh508 400 234 508 312 wqvga (480x234) 15.734 60 fh610 480 234 610 262 15.625 50 fh610 480 234 610 312 vga (640x480) 31.5 60 f h800 640 480 800 525 31.25 50 fh800 640 480 800 625 wvga (800x480) 31.5 60 fh1056 800 480 1056 525 31.25 50 fh1056 800 480 1056 625
summary t c901 04f g ? 201 5 toshiba corporation page 6 rev.1.0 0 20 15/ 12 / 01 5.2.2 input signal the TC90104FG is equipped with 3 -ch adc for composite video signal , y cbcr signal and r g b signal and y/ c signal input. the input - dynamic - range for adc is designed in avdd x 0.4 [v] with the normal input dynamic range being 1 vp - p (avdd = 2.5 v). be sure to use 0.7 vp - p (1 vp - p x 0.7) with 140ire input when using ntsc as the recommended reference inpu t amplitude. w e recommend that you use 0.7 vp - p with 140ire input for the input amplitude. cvbs, y/c, ycbcr, rgb (d1/d2) signal are processed at mcd block, and rgb (wqvga, vga, wvga) signal are processed at rgb block. 5.2.3 table of input ? output signal in put signal processing output signal input format f h [ k hz] sampling clock [mhz] internal format output clock [mhz] rgb 601 656 hd vd enb cvbs ntsc 15.75/15.734 27 4 : 2 : 2 13.5 / 27 - : 2 : 2 13.5 / 27 - : 2 : 2 13.5 / 27 - : 2 : 2 13.5 / 27 - : 2 : 2 13.5 / 27 - : 2 : 2 13.5 / 27 - : 2 : 2 27 - : 2 : 2 27 - : 2 : 2 13.5 / 27 - : 2 : 2 13.5 / 27 - : 2 : 2 27 - : 2 : 2 27 - : 4 : 4 fh508 : 4 : 4 fh508 : 4 : 4 fh610 : 4 : 4 fh610 : 4 : 4 fh800 : 4 : 4 fh800 : 4 : 4 fh1056 : 4 : 4 fh1056
summary t c901 04f g ? 201 5 toshiba corporation page 7 rev.1.0 0 20 15/ 12 / 01 5.2.4 typical input level of analog input signal fig.1 reference input level to cvbs1(composite video) and cvbs2/y/g(s - video y, componet y) when 100% white (i.e., composite video input) cvbs , y, component - y signal need to input 0.7 vpp when 140ire, and also c signal (s - signal) need to input 0.2 vpp when 40ire. (vdd = 2.5 v , 140ire = 0.7 vpp at ntsc ) when use component - cbcr , cbcr - level is 0.7 vpp for 100%. an above waveform is colo r bar signal of 75% i nput terminal i nput level = vp - p *1 o utput : lsb *2 notes cvbs 0.7 vp - p (500 mvp - p ) 16 - 235 (for 8bit) output at itu - r b t. 656/601 format y 0.7 vp - p (500 mvp - p ) 16 - 235 (for 8bit) output at itu - r b t. 656/601 format c 0.2 vp - p (burs t signal) 31 - 225 (for 8bit) output at itu - r b t. 656/601 format cb 0.7 vp - p 31 - 225 (for 8bit) output at itu - r b t. 656/601 format cr 0.7 vp - p 31 - 225 (for 8bit) output at itu - r b t. 656/601 format *1 about input level, it has indicate the case of ntsc. cvbs and y input level will be 140ire at the white of 100%. please adjust to 0.7 v this 100%. values in the ( ) is the level of from the pedestal to white 100 %. input level of c(= chroma signal) has indicate the burst level at the time of ntsc. input level of cbcr has indicate the level of color - 100% at the time of ntsc. *2 about output level, it has indicate the case of ntsc. cvbs and y output level is white100% output level at the time of ntsc. values in the ( ) is the output level of from the ped estal to white 100 %. out put level of c( chroma signal) indicate the cbcr level at the time of color - 100%. output level of cbcr indicate the level of color - 100% at the time of ntsc. notes : th e above output level is influenc ed by the picture quality adjus tment. i t does not indicate the maximum level. 100 -40 0 20 40 60 80 -20 256 51 767 0 1023 avdd0.4v 0.7vp-p
summary t c901 04f g ? 201 5 toshiba corporation page 8 rev.1.0 0 20 15/ 12 / 01 39 0 255 128 217 0.7vp-p 8 0 255 186 0.7vp-p 103 0 255 153 128 0 20 -20 ire 0.2vp-p
summary t c901 04f g ? 201 5 toshiba corporation page 9 rev.1.0 0 20 15/ 12 / 01 5.2.5 operation mode ( i/o select ) setting signal process path (i/o) is selected by i 2 c - bus register (sub00h [d7] rgb_mcd by common on all bank). rgb _ mcd = 0 : mcd block select (cvbs, y/c, y cb cr, rgb(d2,d1) ) 1 : rgb block select (rgb (qvga, vga, wvga) ) output format decides by signal process route. itu - r b t. 601 or itu - r b t. 656 is output at route of mcd block, and rgb 18b it is output at route of rgb block. the setting of mcd block depend on bank0, and setting of rgb depend on bank1 and bank2. i nput mode setting of sub address : 00h active bank s etting contents video 00(hex) bank 0 cvbs/ycbcr input to itu - r b t. 656/601 o utput a - rgb 81(hex) bank1 rgb(dot by dot) input to rgb 18bit output gamma of a - rgb 82(hex) bank2 rgb(dot by dot) input to rgb gamma setting 0.3vp - p
summary t c901 04f g ? 201 5 toshiba corporation page 10 rev.1.0 0 20 15/ 12 / 01 5.2.6 output format the output format (itu - r bt.656/601) is selected by register form at o (bank0, sub address02h). however, when d2 format is inputted, output format is fixed on 4 : 2 : 2 format. y: pedestal level = 16 lsb c : center electric potential = 128 lsb signal process of y output signal below pedestal is set by register clp (bank 0, sub address 29h). clp = 1 : signal below pedestal is fixed on 16lsb clp = 0 : signal below pedestal is outputted through output signal bit data rate description y [0 - 7] 8 13.5 mhz/27 mhz ( itu - r bt. 601/656) y / ycbcr (itu - r bt.601/656) c [0 - 7] 8 6.75 mhz cb / cr (clk : 13 .5 mhz) clk 1 13.5 mhz/27 mhz 864fh/1728fh : 625 line system 858fh/1716fh : 525 line system polarity : negative (initial setting) hd 1 f h recovered horizontal sync signal vd 1 f v recovered vertical sync signal hd / vd pulse width in ?syn c - through? mode 525i system 625i system hd pulse width 4.74
summary t c901 04f g ? 201 5 toshiba corporation page 11 rev.1.0 0 20 15/ 12 / 01 5.2.6.1. 525i / 60hz input mode (1 ? st field) (2nd field) vd position is dependent on register setting. 263 26 4 265 266 267 268 269 270 271 272 273 ? 282 hd out vd out 525 1 2 3 4 5 6 7 8 9 10 ? 19 20 hd out vd out output image output image even odd odd even
summary t c901 04f g ? 201 5 toshiba corporation page 12 rev.1.0 0 20 15/ 12 / 01 5.2.6.2. 6 25i / 5 0hz input mode (1st, 3rd field) (2nd, 4th field) vd position is dependent on register setting. 621 622 623 624 625 1 2 3 4 5 6 ? 22 23 output image hd out vd out 309 310 311 312 hd out vd out output image 319 even odd odd even 314
summary t c901 04f g ? 201 5 toshiba corporation page 13 rev.1.0 0 20 15/ 12 / 01 5.3 rgb block 5.3.1 sync separation t here are two ways to provide sync signal; o ne way is to in put sync -on- green signal to ? c - sync/hd in ? (61pin) and operate sync - separation in ic. another way is to input hd pulse to ? c - sync/hd in ? (61pin) and input vd pulse to ? vd in ? (62 pin). ?c - sync/hd ? (61pin) is an analog slicer input with a sync tip clamping . t he slice level is programmable through the syncslev1[1 : 0] (bank1, sub address 1eh) 5.3.2 detection function for format discrimination following data can be detected for format discrimination by analog/digital sync input signal. no- signal detect, input ana log/digital detect, polarity, detect v frequency, v - sync width, v - sync line, 1v line, h frequency, h - sync width 5.3.3 clock phase adjustment sampling clock of adc can be selected from four phases for each r and g, b channel respectively. 5.3.4 output format output format of video signal, at rgb block path, is 18bit digital rgb signal (r : 6 bit, g : 6 bit, b : 6 bit). also, hd/vd signal is outputted to hd (17 pin) / vd(16 pin), enable signal is outputted to enb (15 pin) and clock signal is outputted to clk (18 pin) .
summary t c901 04f g ? 201 5 toshiba corporation page 14 rev.1.0 0 20 15/ 12 / 01 6. absolute maximum rating the maximum ratings are rated values which must not be exceeded during operation, even for an instant. exceeding the maximum rating may result in destruction, degradation or other damage to the ic and other components. when de signing applications for this ic, be sure that none of the maximum rating values will ever be exceeded. characteristics symbol rating unit power voltage1 (1.5 v system) vdd1 - 0.3 to vss+2.0 v power voltage2 (2.5 v system) vdd2 - 0.3 to vss+3.5 v power voltage3 ( 3.3 v system) vdd3 - 0.3 to vss+3.9 v input voltage ( 1.5 v system) vin1 - 0.3 to vdd 1 +0.3 v input voltage ( 2.5 v system) vin2 - 0.3 to vdd 2 +0.3 v input voltage ( 3.3 v system) vin3 - 0.3 to vdd 3 +0.3 v input voltage ( 3.3 v system, 5 v withsta nd voltage) vin4 (note s 1) - 0.3 to vss+5.5 v potential difference between power pins (between 1.5 v system power pins) vdg1 (note s 2) 0.3 v potential difference between power pins (between 2.5 v system power pins) vdg2 (note s 2 ) 0.3 v potential difference between power pins (between 3.3 v system power pins) vdg3 (note s 2 ) 0.3 v power dissipation pd (note s 3 ) 2190 mw s torage temperature tstg - 40 to 125 c note1 : the withstand voltage for pins (sda, scl) is 5 v. note2 : for each of 1. 5 v and 2.5 v and 3.3 v, system power supply terminal is made into the same voltage . the maximum potential difference should not exc eed rating for all power supply terminals then. in addition, potential difference between all v ss terminal must be under 0.01 v in this status. note 3 : if you intended to use a temperature higher than ta = 25c, reduce by 21.9 mw per one degree (c) inc rease. 7. operating condition the TC90104FG is not guaranteed to function correctly if it is used outside its specified power voltage rage (1.5 v system power : 1.40 v to 1.60 v, 2.5 v system power : 2.3 v to 2.7 v, 3.3 v system power : 3.0 v to 3.6 v). ple ase use within the specified operating conditions. if you temporarily leave and then return to the specified operating conditions, this ic?s conditions will change, and so it is necessary to reset the ic?s power to continue using it correctly within the sp ecified operating conditions. characteristics corresponding terminal symbol min typ. max unit power voltage of digital block 10, 23, 37 vdd -d 1.4 1.5 1.6 v power voltage of i/o block 19, 26, 43 vdd -io 3.0 3.3 3.6 v power voltage of xo block 6 vddxo 2.3 2.5 2.7 v power voltage of pll block 3 vddpll 2.3 2.5 2.7 v power voltage of analog block 1, 49, 58 vddda, vddad 2.3 2.5 2.7 v operating templature topr -40 h 85 c
summary t c901 04f g ? 201 5 toshiba corporation page 15 rev.1.0 0 20 15/ 12 / 01 8. electrical ch a racteristic 8.1 dc characteristic ( ta = 25c , 1.5 v system = 1.50 0.1 v, 2.5 v system = 2.50 0.2 v, 3.3 v system = 3.30 0.3 v) characterist i c terminal no. symbol min typ. max unit note power supply current 10, 23, 37 idd1 (1.5 v system ) 46 70 ma d epend on load at 3.3 v system. 1, 3, 6, 49, 58 idd2 (2.5 v system ) 82 125 ma 19, 26, 43 idd3 (3.3 v system ) 10 ma input voltage 13, 46, 47, 48, 61, 62 vih vdd3x0.8 vdd 3 v i/o input terminal of 3.3 v system 11, 12 i/o input terminal of 5.0 v system 13, 46, 47, 48, 61, 62 vil vss vdd3x0.2 v i/o input terminal of 3.3 v system 11,12 i/o input terminal of 5.0 v system input current 13, 46, 47, 48, 61, 62 iih - 10 10 a i/o input terminal of 3.3 v system 11, 12 i/o input terminal of 5.0 v system 13, 46, 47, 48, 61, 62 iil - 10 10 a i/o input terminal of 3.3 v system 11, 12 i/o input terminal of 5.0 v system output voltage 15, 16, 17, 18, 20, 21, 24, 25, 27, 28, 30, 31, 32, 33, 35, 36, 3 8, 39, 41, 42, 44, 45 v oh vdd3 - 0.6 vdd3 v i/o out put terminal of 3.3 v system w hen l oad current : - 4 ma v ol vss 0.4 v i/o out put terminal of 3.3 v system w hen l oad current : + 4 ma
summary t c901 04f g ? 201 5 toshiba corporation page 16 rev.1.0 0 20 15/ 12 / 01 9. package lqfp64 - p - 1010 - 0.5 0 e unit : mm weight : 0.4 g ( typ. )
summary t c901 04f g ? 201 5 toshiba corporation page 17 rev.1.0 0 20 15/ 12 / 01 10. revision history date revisi on contents 2015 / 12 / 01 1.0 0 first edition
summary t c901 04f g ? 201 5 toshiba corporation page 18 rev.1.0 0 20 15/ 12 / 01 restrictions on p roduct use ? toshiba corporation, and its subsidiaries and affiliates (collectively "toshiba"), reserve the right to make changes to the i nformation in this document, and related hardware, software and systems (collectively "product") without notice. ? thi s document and any information herein may not be reproduced without prior written permission from toshiba. even with toshiba' s written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works conti nually to improve product's quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, softwar e and systems which minimize ri sk and avoid situations in which a malfunction or failure of product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the prod uct, or incorpor ate the product into their own applications, customers must also refer to and comply with (a) the latest versions of all rele vant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes f o r product and the precautions and conditions set forth in the "toshiba semiconductor reliability handbook" and (b) the instructions for the application with which the product will be used with or for. customers are solely responsible for all aspects of the ir own product design or applications, including but not limited to (a) determining the appropriateness of the use of this product in such design or a pplications; (b) evaluating and determining the applicability of any information contained in this documen t, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. toshiba assumes no liability for customers' product design or ap plications. ? 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